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ds04-31102-1e fujitsu semiconductor data sheet assp for graphics control graphics display controller MB86291A n n n n description the MB86291A is an evolved version of the fujitsu mb86290a graphics controller designed for use in a car navigation system or amusement equipment. the MB86291A is a graphics display controller with a geometry processor, digital video capture facility, and on-chip sdram. embedding sdram implements data transfer at a higher bandwidth, resulting in faster drawing. integrating the geometry processor reduces the cpu load, thereby improving the performance of the entire system. n n n n featuers ? operating frequency : 100 mhz (external clock of 14.32 mhz max) ? geometry processor: capable of executing operations for geometric transformation and surface front/rear evaluation. ? memory block: embedded 16-mbit sdram ? video capture block: embedded facility to capture digital video images, for example, from tv, capable of easily implementing picture in picture and video graphics superimposing. ? host interface: enables direct connection to various cpus (fujitsu sparclite, hitachi sh3/4 or nec v83x) . (continued) n n n n pac k ag e 208-pin plastic qfp (fpt-208p-m04)
MB86291A 2 (continued) ? drawing features: drawing at a peak rate of 800 mpixels per second (at an internal operating frequency of 100 mhz) 2d drawing functions: point, line, triangle, polygon, blt, and pattern drawing 3d drawing functions: point, line, and triangle drawing, and hidden surface removal by z-buffering special effects: anti-aliasing, bold/dashed-line processing, alpha blending, gouraud shading, texture mapping (bilinear filtering, perspective correct) , and tiling ? display features : maximum display resolution supported : 1024 768 pixels color display either with a color palette of 8 bits per pixel or directly using 5-bit rgb colors of 16 bits per pixel overlaying four layers of screen, of which two lower layers can be divided into the left and right parts supporting two 64 64-pixel hardware cursors output of analog rgb and digital rgb signals capable of superimposing using an external synchronization mode ? power-supply voltage : two power supplies at 2.5 v 0.2 v for internal circuits and sdram, and 3.3 v 0.2 v for i/o parts ? package: plastic qfp with 208 pins (with a lead pitch of 0.5 mm) ? process technology : 0.25 m m cmos
MB86291A 3 n n n n pin assignment acompr 156 vro 154 avd3 153 aoutr 152 avs3 151 avs2 150 acompg 145 avs0 144 aoutb 143 avd0 142 acompb 141 vddi 139 a7 138 a6 137 a5 136 a4 135 a3 134 a2 133 vddi 132 vss 131 pllvss 130 s 129 oscout 128 pllvdd 127 vdde 126 vss 125 clk 124 osccnt 123 vss 122 vddi 121 we3 120 we2 119 we1 118 we0 117 rd 116 bs 115 cs 114 bclki 113 vddi 112 vss 111 vdde 110 open 109 dtack/tc 108 drack/dmaak 107 ckm 106 testh4 105 vss 140 avd2 149 avs1 148 aoutg 147 avd1 146 vref 155 1 3 4 5 6 7 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 17 8 9 10 11 2 vss r0 r1 vcc1 vss r2 r7 vcc2 vdde vss vcc3 g0 g1 g2 g3 vss g4 g5 g6 g7 vdde b0 b1 b2 b3 vss b4 b5 b6 b7 vcc4 vddi vss vcc5 vdde clksel0 clksel1 reset mode0 mode1 vss vcc6 mode2 testl0 vcc7 vss vddi r3 r4 r5 r6 vcc0 vss 208 hsync 206 vsync 205 csync 204 vss 203 dclko 202 vdde 201 vi7 200 vi6 199 vi5 198 vi4 197 vi3 196 vi2 195 vi1 194 vi0 193 vddi 192 vss 191 dclki 190 eo 189 reserve 188 reserve 187 gv 207 reserve 186 reserve 184 testh5 183 cclk 182 vdde 181 vss 180 a24 179 a23 178 a22 a21 177 a20 176 a19 175 a18 174 a17 173 a16 172 vddi 171 vss 170 a15 169 a14 168 a13 167 a12 166 reserve 185 a11 165 a9 163 a8 162 testl1 161 vdde 160 vddi 159 158 157 vss a10 164 testh0 vddi d0 d1 d2 d3 d4 d5 d6 d7 vdde vss d8 d9 d10 d11 d12 d13 d14 vddi vss vss d15 d17 d18 vdde d19 d20 d21 d22 d23 d24 vss vddi d25 d26 d27 d28 d29 vss vdde d30 d31 d16 rdy int vss vddi testh1 testh2 testh3 dreq 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 54 75 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 76 96 98 99 100 101 102 103 104 97 (top view) vss/avs/pllvss vddh/vdde vddl/avd/pllvdd/vcc/vddi avd pllvdd vcc open testl0/testl1 testh0 ~ testh5 reserve notes : the avd and pllvdd should be separated on the board. insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. place the capacitor as near the pins as possible. : ground : 3.3 v power supply : 2.5 v power supply : analog power supply : pll power supply : internal dram power supply : do not connect anything. : input the low level. : input the high level. : input the high level.
MB86291A 4 n n n n pin description d0-d31 a2-a24 bclki reset cs rd we0-we3 rdy bs dreq drack dtack int testl, testh clk s ckm oscout osccnt dclko dclki hsync vsync csync eo gv vref vro r0-r7 g0-g7 b0-b7 cclk vi0-vi7 MB86291A graphics controller hqfp208 acompr, acompg, acompb aoutr, aoutg, aoutb clksel0- clksel1 mode0- mode2 vide output interface host cpu interface clock vide capture interface
MB86291A 5 host interface pins note : the host interface can connect the MB86291A to the sh4 (sh7750) or sh3 (sh7709) from hitachi ltd. the v832 from nec, or to the sparclite (mb86833) from fujitsu without any external circuit in between. (using the sram interface allows the MB86291A to use another cpu.) the host cpu is set by the mode0 and mode1 pins as shown below. note : the mode2 pin can be used to set the ready signal level to be used upon completion of the bus cycle. to use the mode2 signal at "h" level, set the software setting to two cycles. pin name input/output function mode0 to mode2 input host cpu mode/ready mode select reset input hardware reset d0 to d31 input/output host cpu bus data a2 to a24 input host cpu bus address (connect a[24] to mwr in v832 mode.) bclki input host cpu bus clock bs input bus cycle start signal cs input chip select signal rd input read strobe signal we0 input d0 to d7 write strobe signal we1 input d8 to d15 write strobe signal we2 input d16 to d23 write strobe signal we3 input d24 to d31 write strobe signal rdy output tristate wait request signal (0 for wait state with sh3; 1 for wait state with sh4, v832, or sparclite) dreq output dma request signal (active low with both sh and v832) drack/dmaak input dma request acknowledge signal (connect this to dmaak in v832 mode. active high with both sh and v832.) dtack/tc input dma transfer strobe signal (connect this to tc in v832 mode. sh = active high, v832 = active low) int output host cpu interrupt signal (sh = active low, v832 = active high) test0, test1, testh0 to testh5 input test signal mode1 pin mode0 pin cpu type llsh3 lhsh4 hlv832 h h sparclite mode2 pin ready signal mode l set rdy signal to "not ready" level upon completion of bus cycle. h set rdy signal to "ready" level upon completion of bus cycle.
MB86291A 6 notes : the host interface transfers data signals at a fixed width of 32 bits. there are 23 lines for address signals handled in double words ( = 32 bits) and 32 mbytes of address space. the external bus can be used at an operating frequency of 100 mhz maximum. the rdy signal at the low level sets the ready state in the sh4 or v832 mode; the signal at the low level sets the wait state in the sh3 mode. note that the rdy signal is a tristate output. the host interface supports dma transfer using an external dma controller. the host interface generates a host processor interrupt signal. the reset pin requires low level input of at least 300 m s after setting s (pll reset signal) to high level. fix the test signal at high level. in the v832 mode, connect the following pins as specified : vide output interface notes : the video output interface contains an 8-bit d/a converter to output analog rgb signals. also, the eight-bit rgb digital output pins can connect an external digital video encoder. using an additional external circuit, the video output interface can generate composite video signals. the video output interface can provide display synchronized with external video. the mode for synchronization with the dclki signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. scarlet pin name v832 signal name a24 mwr dtack tc drack dmaak pin name input/output function dclko output display dot clock signal output dclki input dot clock signal input hsync input/output horizontal sync signal output horizontal sync signal input in external synchronization mode vsync input/output vertical sync signal output vertical sync signal input in external synchronization mode csync output composite sync signal output eo input even/odd-number field identification input gv output graphics/video select signal r0-r7 output digital video (r) signal output g0-g7 output digital video (g) signal output b0-b7 output digital video (b) signal output aoutr analog output analog video (r) signal output aoutg analog output analog video (g) signal output aoutb analog output analog video (b) signal output vref analog reference voltage input pin acompr analog r-signal compensation pin acompg analog g-signal compensation pin acompb analog b-signal compensation pin vro analog reference current setting pin
MB86291A 7 the hsync and vsync signals must be pulled up outside the lsi as they enter the input state upon reset. terminate the aoutr, aoutg, and aoutb pins with a resistance of 75 w . input 1.1 v to the vref pin. between this pin and analog ground, insert a bypass capacitor (one with a superior high-frequency characteristic such as a laminated ceramic capacitor). connect the acompr, acompg, and acompb pins to the 0.1 m f ceramic capacitor ahead of the analog power supply. connect the vro pin to the analog ground with a 2.7 k w resistor. for noninterlaced display in external synchronization mode, input "0" to the eo pin, for example, using a pull-down resistor. the gv signal serves to switch between graphics and video for chroma keying. the pin outputs a low level signal to select video.
MB86291A 8 video capture interface note : the video capture interface inputs digital video signals in the itu-rbt-656 format. clock input *1 : do not connect anything. *2 : input the h level. notes : the clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. usually input 4 fsc ( = 14.31818 mhz) . the internal pll generates the internal operating clock signal of 100 mhz and the display reference clock signal of 200 mhz. the internal operating clock signal to be used can be selected between the clock signal (100 mhz) generated by the internal pll and the bus clock bclki input to the host cpu interface. select the bclki input to use the host cpu bus at 100 mhz. note : use the clksel pin to select the input clock frequency for using the internal pll with ckm = l. note : immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the s pin before setting it to high level. after the s signal goes high, input the reset signal at low level for 300 m s or more pin name input/output function cclk input digital video input clock signal input vi0-vi7 input digital video data input pin name input/output function clk input clock input signal s input pll reset signal ckm input clock mode signal clksel1, clksel0 input clock rate select signal oscout* 1 input/output for connection of crystal oscillator (reserved) osccnt* 2 input for selection of crystal oscillator (reserved) ckm clock mode l select internal pll output. h select host cpu bus clock (bclki) clksel1 clksel0 clock frequency l l input 13.5 mhz. l h input 14.32 mhz. h l input 17.73 mhz. hhreserved
MB86291A 9 n n n n block diagram host interface display controller external video interface controller rbt656 geometry engine 2d/3d rendering engine memory interface controller d0-d31 a2-a24 drgb argb dac embedded sdram
MB86291A 10 n n n n function blocks host interfacee this block allows the MB86291A to be connected to the sh3 or sh4 microprocessor from hitachi ltd., the v83x microprocessor from nec, or to the sparclite from fujitsu without any external circuit in between. the block provides an interface to transfer display list and texture pattern data directly from main memory to this devices graphics memory or internal register using the external dma controller. memory interface controller and embedded sdram the embedded 16-megabit sdram eliminates the need for external memory. the sdram operates at 100 mhz. display controller this block contains a three-channel, eight-bit d-a converter to output analog rgb signals. the block has eight- bit rgb digital video outputs, allowing an external digital video encoder to be connected. the block supports resolutions of up to xga (1024 768 pixels), enabling flexible setting. external video interface controller this block can input digital video in the itu rbt-656 format by connecting an external digital video decoder using the eight-bit video input pin. input video data is stored temporarily in graphics memory and then displayed on the screen in synchronization with the display scan. the block supports video in the ntsc and pal formats. set-up engine the on-chip geometry engine executes mathematical operations required for graphics processing precisely using the fronting-point format. the geometry engine executes the required geometry processes selected depending on the drawing mode and primitive type settings up to the final drawing process. 2d/3d rendering engine this block draws images in two or three dimensions. ?2d drawing the block provides the anti-aliasing and alpha blending functions to display high-quality images even on a low- resolution lcd. ?3d drawing the block provides true 3d drawing functions such as perspective texture mapping and gouraud shading.
MB86291A 11 n n n n absolute maximum ratings *1 : the analog and pll power supplies are included. *2 : model supporting a wider range of temperatures warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating condition *1 : the analog and pll power supplies are included. *2 : aoutr, aoutg and aoutb pins *3 : acompr, acompg, and acompb pins parameter symbol rating unit min max power supply voltage v ddl * 1 - 0.5 + 3.0 v v ddh - 0.5 + 4.0 input voltage v i - 0.5 v ddh + 0.5 ( < 4.0) v output current i o - 13 + 13 ma power pin current i pow ? 60 ma ambient operating temperature t a 0 + 70 c - 30* 2 + 85* 2 ambient storage temperature tstg - 55 + 125 c parameter symbol value unit min typ max power supply voltage v ddl * 1 2.3 2.5 2.7 v v ddh 3.0 3.3 3.6 v input voltage (high level) v ih 2.0 ? v ddh + 0.3 v input voltage (low level) v il - 0.3 ? + 0.8 v vref pin input voltage v ref 1.05 1.10 1.15 v vro pin external resistor r vro ? 2.7 ? k w aout pin external resistor* 2 r aout ? 75 ?w acomp pin external capacitor* 3 c acomp ? 0.1 ?m f ambient operating temperature t a - 40 ? + 85 c
MB86291A 12 notes : the vddl and vddh power supplies can be turned on or off in either order. note, however, that the vddh voltage must not be applied alone continuously for several seconds. after turning the power on, input a pulse remaining at low level for at least 500 ns to the s pin. then, set the s pin to high level and input the reset signal held at low level for at least 300 m s. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
MB86291A 13 n n n n electrical characteristics 1. dc characteristics v ddl = 2.5 v 0.2 v, v ddh = 3.3 v 0.3, v ss = 0.0 v, t a = 0 c to + 70 c *1 : value when - 100 m a current flows into output pins. *2 : value when 100 m a current flows into output pins. *3 : output characteristics of int , dreq, and rdy *4 : output characteristics of the signals (excluding analog signals) other than those in *3 *5 : aoutr, aoutg, and aoutb pin output current. condition v ref = 1.10 v, r vro = 2.7 k w (the full-scale output current calculation expression is (v ref / r vro ) 25.575) *6 : aoutr, aoutg, and aoutb pins parameter symbol value unit min typ max output voltage (high level) * 1 v oh v ddh - 0.2 ? v ddh v output voltage (low level) * 2 v ol 0.0 ? 0.2 v output current (high level) i ohm * 4 - 4.0 ?? ma i ohh * 3 - 8.0 output current (low level) i olm * 4 4.0 ?? ma i olh * 3 8.0 aout output current* 5 full scale i aout 9.90 10.42 10.94 ma zero scale 0 2 20 m a aout voltage* 6 v aout - 0.1 ?+ 1.1 v input leakage current i l ?? 5 m a pin capacitance c ?? 16 pf
MB86291A 14 2. ac characteristics (v ih = 2.0 v, v il = 0.8 v) (v ih + v il ) / 2 t r 80% 20% 80% 20% v ih v il t f v ih v oh v ol v ol v oh v il 0.5 v 0.5 v (v ih + v il ) /2 t phl , t pzl t plh , t pzh t plz t phz v dd /2 v dd /2 input measurement conditions output measurement conditions tr, tf 5 ns input measurement standard : (vih + vil) / 2 input input output 1 output 2 output 3 output measurement standard : t plz : v ol + 0.5 v t phz : v oh - 0.5 v else : v dd /2
MB86291A 15 (1) host interface clock signals host interface signals (external load of 20 pf) *1 : hold time for reset cancellation *2 : read data is output one cycle before the cpu samples it. parameter symbol condi- tion value unit min typ max bclki frequency f bclki ?? ? 100 mhz bclki h period t hbclki ? 1 ?? ns bclki l period t lbclki ? 1 ?? ns parameter symbol condi- tion value unit min typ max address setup time t ads ? 4 ?? ns address hold time t adh ? 0 ?? ns bs setup time t bss ? 3 ?? ns bs hold time t bsh ? 0 ?? ns cs setup time t css ? 3 ?? ns cs hold time t csh ? 0 ?? ns rd setup time t rds ? 3 ?? ns rd hold time t rdh ? 0 ?? ns we setup time t wes ? 5 ?? ns we hold time t weh ? 1 ?? ns write data setup time t wds ? 3 ?? ns write data hold time t wdh ? 0 ?? ns dtack setup time t daks ? 3 ?? ns dtack hold time t dakh ? 0 ?? ns drack setup time t drks ? 3 ?? ns drack hold time t drkh ? 0 ?? ns read data delay time (to rd ) t rddz ? 3.0 ? 11.0 ns read data delay time t rdd *2 4.5 ? 10.5 ns rdy delay time (to cs ) t rdydz ? 2.5 ? 5.0 ns rdy delay time t rdyd ? 2.5 ? 6.0 ns int delay time t intd ? 3.0 ? 6.5 ns dreq delay time t drqd ? 2.5 ? 6.0 ns mode hold time t modh *1 ?? 20.0 ns
MB86291A 16 clock input setup and hold times read/write enable (rd , we ) and input data (d) setup times bclki 1/f bclki t hbclki t lbclki bclki a2~a24, bs, cs, dtack, drack t ads , t bss , t css , t daks , t drks t adh , t bsh , t csh , t dakh , t drkh bclki bs d0~d31 t wds t wdh rd, we t rds , t wes t rdh, t weh
MB86291A 17 dreq output delay time int output delay time rdy delay value (with respect to cs ) bclki dreq (output) t drqd bclki int (output) t intd bclki cs rdy (output) high-z high-z t rdydz t rdydz
MB86291A 18 rdy /d output delay values mode signal hold time bclki rd rdy t rddz t rdd t rdyd t rdyd d0~d31 (output) high-z output data reset mode0~ mode2 t modh
MB86291A 19 (2) video interface clock input signals *1 : applied only in pll synchronization mode (cks = 0) . the reference clock is the internal plls output with cycle = 1/ (14 f clk ) . *2 : applied only in dclki synchronization mode (cks = 1) . the reference clock is dclki. *3 : based on the edge with vsync negated. output signals * : the eo output varies at the same time as vsync is asserted. parameter symbol condi- tion value unit min typ max clk frequency f clk ?? 14.32 ? mhz clk h period t hclk ? 25 ?? ns clk l period t lclk ? 25 ?? ns dclki frequency f dclki ?? ? 67 mhz dclki h period t hdclki ? 5 ?? ns dclki l period t ldclki ? 5 ?? ns dclko frequency f dclko ?? ? 67 mhz parameter symbol condi- tion value unit min typ max hsync input pulse width t whsync0 *1 3 ?? clock t whsync1 *2 3 ?? clock hsync input setup time t shsync *2 10 ?? ns hsync input hold time t hhsync *2 10 ?? ns vsync input pulse width t whsync1 ? 1 ?? hsync 1 cycle eo input setup time t seo *3 10 ?? ns eo input hold time t heo *3 10 ?? ns parameter symbol condi- tion value unit min typ max eo output delay time t deo *1.5 ? 11 ns hsync output delay time t dhsync ? 1.5 ? 11 ns vsync output delay time t dvsync ? 1.5 ? 11 ns csync output delay time t dcsync ? 1.5 ? 11 ns gv output delay time t dgv ? 1.5 ? 11 ns
MB86291A 20 clock hsync signal setup and hold eo signal setup and hold output signal delay clk 1/f clk t hclk v ih v il t lclk dclki hsync (input) 1/f dclki t hdclki t ldclki t shsync t hhsync vsync eo (input) t seo t heo dclko eo (output) hsync (output) vsync (output) csync gv t deo , t dhsync , t dvsync , t dcsync , t dgv
MB86291A 21 (3) video capture interface clock input signals clock video input parameter symbol condi- tion value unit min typ max cclki frequency f cclki ?? 27 ? mhz cclki h period t hcclki ? 1 ?? ns cclki l period t lcclki ? 1 ?? ns parameter symbol condi- tion value unit min typ max vi setup time (external load of 25 pf) t vis ? 11 ?? ns vi hold time (external load of 15 pf) t vih ? 2 ?? ns clk 1/f clk t hclk t lclk v ih v il cclki vi0~vi7 t vis t vih
MB86291A 22 (4) pll standards parameter value unit remarks min typ max input frequency ? 14.31818 ? mhz output frequency ?? 200.45452 mhz multiplied by 14 duty ratio 93.1 ? 101.3 % pll output clock h/l pulse width ratio jitter - 150 ?+ 180 ps cycle difference between two consecutive cycles
MB86291A 23 n n n n ordering information part number package remarks MB86291Apfvs 208-pin plastic qfp (fpt-208p-m04)
MB86291A 24 n n n n package dimension 208-pin plastic qfp (fpt-208p-m04) note : pins width and pins thickness include plating thickness. dimension in mm (inches) c 2000 fujitsu limited f208020s-c-2-3 .148 ?012 +.008 ?.30 +0.20 3.75 details of "a" part 0.50?.20 (.020?008) 0.60?.15 (.024?006) 0.25(.010) (stand off) 0.40 +0.10 ?.15 +.004 ?006 .016 0?8 1 lead no. 52 53 104 105 156 157 208 "a" 0.08(.003) 0.50(.020) 0.22?.05 (.009?002) 0.08(.003) m 28.00?.10(1.102?004)sq 30.60?.20(1.205?008)sq .007 ?003 +.001 ?.08 +0.03 0.17 index (mounting height)
MB86291A fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0203 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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